v 20111231 2 C 40000 40000 0 0 0 title-B.sym C 46000 48700 1 180 1 DB25-2.sym { T 47400 43350 5 10 0 0 180 6 1 device=DB25 T 46600 43100 5 10 1 1 180 6 1 refdes=X1 } N 46000 45300 45200 45300 4 N 45200 48100 45200 42700 4 N 46000 45700 45200 45700 4 N 46000 46100 45200 46100 4 N 46000 46500 45200 46500 4 N 46000 46900 45200 46900 4 N 46000 47300 45200 47300 4 N 46000 47700 45200 47700 4 N 46000 48100 45200 48100 4 N 45200 42700 54000 42700 4 T 46200 49200 9 10 1 0 180 6 1 Dsub 25 pol hane T 41700 40900 9 10 1 0 0 0 1 Source: http://wiki.openwrt.org/doc/hardware/port.jtag.cable.unbuffered N 47500 43900 48900 43900 4 N 48900 43900 48900 46600 4 N 48900 46600 49300 46600 4 N 48000 48300 48000 46300 4 N 48000 46300 50600 46300 4 N 47500 44300 48600 44300 4 N 48600 44300 48600 45700 4 N 48600 45700 50600 45700 4 C 49300 46500 1 0 0 Res_H-2.sym { T 49200 46700 5 10 1 1 0 0 1 refdes=R1 T 49300 48000 5 10 0 0 0 0 1 device=Resistor T 50100 46700 5 10 1 1 0 0 1 value=100R } N 53600 46900 54000 46900 4 N 54000 42700 54000 46900 4 N 53600 46600 54000 46600 4 N 53600 46300 54000 46300 4 N 53600 46000 54000 46000 4 N 53600 45700 54000 45700 4 C 52400 45400 1 0 0 Connector-2c5r-2.sym { T 53100 47300 5 10 1 1 0 6 1 refdes=X2 T 52700 47500 5 10 0 0 0 0 1 device=Connector } N 52400 46600 50200 46600 4 C 50600 45600 1 0 0 Res_H-2.sym { T 50500 45800 5 10 1 1 0 0 1 refdes=R4 T 50600 47100 5 10 0 0 0 0 1 device=Resistor T 51400 45800 5 10 1 1 0 0 1 value=100R } C 49300 45900 1 0 0 Res_H-2.sym { T 49200 46100 5 10 1 1 0 0 1 refdes=R2 T 49300 47400 5 10 0 0 0 0 1 device=Resistor T 50100 46100 5 10 1 1 0 0 1 value=100R } C 50600 46200 1 0 0 Res_H-2.sym { T 50500 46400 5 10 1 1 0 0 1 refdes=R3 T 50600 47700 5 10 0 0 0 0 1 device=Resistor T 51400 46400 5 10 1 1 0 0 1 value=100R } T 52200 46300 9 6 1 0 0 0 1 TDO T 52200 46600 9 6 1 0 0 0 1 TDI T 52200 46000 9 6 1 0 0 0 1 TMS T 52200 45700 9 6 1 0 0 0 1 TCK N 51500 45700 52400 45700 4 N 52400 46000 50200 46000 4 N 49300 46000 48300 46000 4 N 48300 44700 48300 46000 4 N 48300 44700 47500 44700 4 N 51500 46300 52400 46300 4 N 47500 48300 48000 48300 4 T 47700 44300 9 6 1 0 0 0 1 TCK T 47700 44700 9 6 1 0 0 0 1 TMS T 47700 48300 9 6 1 0 0 0 1 TDO T 47700 43900 9 6 1 0 0 0 1 TDI T 41700 41200 9 10 1 0 0 0 1 Unbuffered Cable, Xilinx DLC5 Cable III T 41700 41500 9 10 1 0 0 0 1 Parallel port based JTAG dongle T 52700 45100 9 10 1 0 0 0 1 12 pin header used in the original